18ES624 FPGA BASED SYSTEM DESIGN
Credits: 4 Prerequisites: Digital Systems
THIS PAGE contains information about the subject 18ES624 FPGA Based System Design offered in the Second semester of 2018 - 2019. It tells you everything about this course, including its aim, syllabus, and operation.
· What is this course for?
· What you will learn
· Lecture schedule
· Assignments
· Supplementary materials
· References
· What is this course for?
· What you will learn
· Lecture schedule
· Assignments
· Supplementary materials
· References
What is this course for?
The role of Field Programmable Gate Array (FPGA) in Embedded Systems is gaining importance due to its increasing capabilities and availability of powerful FPGA design software tools. FPGAs enable an optimal balancing of computational resources versus DSP/processors which attempt to provide one solution for all. FPGA flexibility enables the parallelization of DSP processing resources to meet a targeted performance level.
Automotive Infotainment, Automotive driver assistance, Video surveillance, Wired and Wireless communications, defense, medical and test and measurement all use FPGAs to address emerging and changing standards. FPGA power, performance and feature sets address these requirements in ways only ASICs did in the past.
The economic, financial and competitive conditions have forced ASIC and ASSP vendors to refocus their efforts on higher volume markets and applications. This has created a gap in the technical solutions available to these effected markets. FPGAs are uniquely suited to address this gap and the needs of these markets by providing a common reprogrammable solution that can be used by many markets for different purposes. FPGAs can cost effectively what alternative technologies cannot. At the same time the increase in performance, reduction in power consumption and the focus on ease-of-use allow FPGAs to address customer technical requirements.
What you will learn
This course will give you the foundation for FPGA design in Embedded Systems along with practical design skills. You will learn what an FPGA is and how this technology was developed, how to select the best FPGA architecture for a given application, how to use state of the art software tools for FPGA development, and solve critical digital design problems using FPGAs. Emphasis is given on digital design using VerilogHDL and FPGA architectures.
Course Outcomes (COs):
CO1: Realization of combinational logic circuits in circuit level and using PLDs
CO2: Design combinational logic circuits using HDL
CO3: Design sequential logic circuits using HDL
CO4: Understand the design styles in different FPGA architectures
CO5: Synthesize digital circuits in FPGAs
Automotive Infotainment, Automotive driver assistance, Video surveillance, Wired and Wireless communications, defense, medical and test and measurement all use FPGAs to address emerging and changing standards. FPGA power, performance and feature sets address these requirements in ways only ASICs did in the past.
The economic, financial and competitive conditions have forced ASIC and ASSP vendors to refocus their efforts on higher volume markets and applications. This has created a gap in the technical solutions available to these effected markets. FPGAs are uniquely suited to address this gap and the needs of these markets by providing a common reprogrammable solution that can be used by many markets for different purposes. FPGAs can cost effectively what alternative technologies cannot. At the same time the increase in performance, reduction in power consumption and the focus on ease-of-use allow FPGAs to address customer technical requirements.
What you will learn
This course will give you the foundation for FPGA design in Embedded Systems along with practical design skills. You will learn what an FPGA is and how this technology was developed, how to select the best FPGA architecture for a given application, how to use state of the art software tools for FPGA development, and solve critical digital design problems using FPGAs. Emphasis is given on digital design using VerilogHDL and FPGA architectures.
Course Outcomes (COs):
CO1: Realization of combinational logic circuits in circuit level and using PLDs
CO2: Design combinational logic circuits using HDL
CO3: Design sequential logic circuits using HDL
CO4: Understand the design styles in different FPGA architectures
CO5: Synthesize digital circuits in FPGAs
Evaluation
Method of evaluation is by Continuous Assessment and an End-of-Semester examination.
Continuous Assessment - 70%
Periodical Test I - 15%
Periodical Test II - 15%
Quiz/Assignment - 10%
Laboratory - 10%
Mini Project - 20%
End-of-Semester Examination - 30%
Method of evaluation is by Continuous Assessment and an End-of-Semester examination.
Continuous Assessment - 70%
Periodical Test I - 15%
Periodical Test II - 15%
Quiz/Assignment - 10%
Laboratory - 10%
Mini Project - 20%
End-of-Semester Examination - 30%
Suggested Readings
Main Text
1. M.Morris Mano, Michael D.Ciletti, "Digital Design: With an Introduction to VerilogHDL", Pearson, Fifth Ed, 2007
2. Samir Palnitkar, "Verilog HDL: a guide to digital design and synthesis", Prentice Hall, Second Edition, 2003
3. Wayne Wolf, "FPGA based System Design", Prentice Hall, 2004
1. M.Morris Mano, Michael D.Ciletti, "Digital Design: With an Introduction to VerilogHDL", Pearson, Fifth Ed, 2007
2. Samir Palnitkar, "Verilog HDL: a guide to digital design and synthesis", Prentice Hall, Second Edition, 2003
3. Wayne Wolf, "FPGA based System Design", Prentice Hall, 2004
Lecture Schedule
Week
1
2 3
4 5 6 7 8 9 10 11 |
Topics
Introduction to the course
Introduction to digital design Programmable logic Introduction to Verilog HDL, Hierarchical Modeling Concepts, Basic concepts and Modules and Ports
Gate level modeling Switch level modeling Data flow modeling Behavioral modeling Tasks and functions Combinational and Sequential circuit design, State Machine Designs Asynchronous Circuits Logic synthesis with Verilog HDL Introduction to FPGA Fabrics Logic Implementation of FPGA |
Keywords
Role of Field Programmable Gate Arrays (FPGAs) in Embedded system design, Market share of Embedded FPGA, History and architecture of programmable logic devices including FPGAs, difference between an FPGA, a CPLD, an ASSP, an ASIC, Microcontrollers and Digital signal Processors.
Why digital?, components of digital system, logic families - TTL and CMOS equivalent of gates, Need for Minimization, reduction techniques available. Implementation of Combinational circuits, implementation of Combinational circuits with MUX and Memory, Introduction to Sequential logic. Implementation of Combinational circuits with PLDs, limitations of PLDs, implementation using CPLD, Simple PLDs, CPLDs, ASIC/FPGA design flow, HDL, Role of HDL. Evolution of CAD, emergence of HDLs, typical HDL-based design flow, why Verilog HDL?, trends in HDLs, Top-down and bottom-up design methodology, differences between modules and module instances, parts of a simulation, design block, stimulus block.Lexical conventions, data types, system tasks, compiler directives
Modeling using basic Verilog gate primitives, description of and/or and buf/not type gates, rise, fall and turn-off delays MOS and CMOS switches, bidirectional switches, modeling of power and ground, resistive switches, delay specification on switches. Continuous assignments, expressions, operators, operands, operator types. PERIODICAL- I Structured procedures, initial and always, blocking and non-blocking statements, delay control, generate statement, event control, conditional statements, multi-way branching, loops, sequential and parallel blocks, Differences between tasks and functions, declaration, invocation, automatic tasks and functions Code converters, Flip-flops, counters, Shift registers, FIFOMoore and Mealy machine, Design and Analysis Analysis & Synthesis of asynchronous digital circuits, State Reduction, State Assignment, Hazards Introduction to logic synthesis, impact of logic synthesis, Verilog HDL constructs and operators for logic synthesis, synthesis design flow, verification of synthesized circuits, modeling tips, design partitioning. PERIODICAL - II Implementation Technology - PLDs, custom chips, standard cell and gate arrays
Logic implementation by macro, logic synthesis, logic optimization, Physical design for FPGAs END SEMESTER EXAMINATION |
Handouts
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