16PE713 FPGA BASED SYSTEM DESIGN
Credits:3 Prerequisites: Digital Systems
THIS PAGE contains information about the subject 16PE713 FPGA based System Design offered in the Third semester of 2018 - 2019. It tells you everything about this course, including its aim, syllabus, and operation.
· What is this course for?
· What you will learn
· Lecture schedule
· Assignments
· Supplementary materials
· References
· What is this course for?
· What you will learn
· Lecture schedule
· Assignments
· Supplementary materials
· References
What is this course for?
VLSI (Very Large Scale Integration) technology has emerged as a very important technology in modern electronics featuring deep sub micron manufacturing processes, low voltage operations, exploding speeds and smart programmable devices sufficient enough to digest ambient conditions to extremes. The electronics industry worldwide is rapidly approaching another revolutionary leap in the global market scenario. Semiconductor technology has crossed the quarter-micron threshold, making tens of millions of transistors available on a single chip equipped with the powerful arm of VLSI design. This imparts the electronics industry a potential to create designs of incredible densities and lightning speeds. This has had a phenomenal impact on widespread applications ranging from consumer electronics, communications, and defense to just about everything.
What you will learn
The course gives an insight in designing complex digital systems using integrated circuit cells as building blocks and employing hierarchical design methods. Emphasis is given on digital design using VerilogHDL and FPGA architectures. A design tour of FPGA using Xilinx ISE tool will also be introduced.
What you will learn
The course gives an insight in designing complex digital systems using integrated circuit cells as building blocks and employing hierarchical design methods. Emphasis is given on digital design using VerilogHDL and FPGA architectures. A design tour of FPGA using Xilinx ISE tool will also be introduced.
Evaluation
Method of evaluation is by Continuous Assessment and an End-of-Semester examination.
Continuous Assessment - 50%
Periodical Test I - 15%
Periodical Test II - 15%
Quiz/tutorial - 5%
Mini Project - 15%
End-of-Semester Examination - 50%
Method of evaluation is by Continuous Assessment and an End-of-Semester examination.
Continuous Assessment - 50%
Periodical Test I - 15%
Periodical Test II - 15%
Quiz/tutorial - 5%
Mini Project - 15%
End-of-Semester Examination - 50%
Suggested Readings
Main Text
1. Samir Palnitkar, "Verilog HDL: a guide to digital design and synthesis", Prentice Hall, Second Edition, 2003
2. Wayne Wolf, "FPGA based System Design", Prentice Hall, 2004
1. Samir Palnitkar, "Verilog HDL: a guide to digital design and synthesis", Prentice Hall, Second Edition, 2003
2. Wayne Wolf, "FPGA based System Design", Prentice Hall, 2004
Lecture Schedule
Week
1
2 3
4 5
6 7 8 9 10 11 |
Topics
Introduction to digital design
Programmable logic Introduction to Verilog HDL, Hierarchical Modeling Concepts, Basic concepts and Modules and Ports
Gate level modeling Switch level modeling
Data flow modeling Behavioral modeling Tasks and functions Combinational and Sequential circuit design, State Machine Designs Logic synthesis with Verilog HDL Introduction to FPGA Fabrics Logic Implementation of FPGA Architecture and Large Scale Systems |
Keywords
Why digital?, components of digital system, logic families - TTL and CMOS equivalent of gates, Need for Minimization, reduction techniques available, Implementation of Combinational circuits, implementation of Combinational circuits with MUX and Memory
implementation of Combinational circuits with PLDs, limitations of PLDs, implementation using CPLD, Simple PLDs, CPLDs, ASIC/FPGA design flow, HDL, Role of HDL. Evolution of CAD, emergence of HDLs, typical HDL-based design flow, why Verilog HDL?, trends in HDLs, Top-down and bottom-up design methodology, differences between modules and module instances, parts of a simulation, design block, stimulus block.Lexical conventions, data types, system tasks, compiler directives
Modeling using basic Verilog gate primitives, description of and/or and buf/not type gates, rise, fall and turn-off delays PERIODICAL-I MOS and CMOS switches, bidirectional switches, modeling of power and ground, resistive switches, delay specification on switches. Continuous assignments, delay specification, expressions, operators, operands, operator types. Structured procedures, initial and always, blocking and non-blocking statements, delay control, generate statement, event control, conditional statements, multi-way branching, loops, sequential and parallel blocks, Differences between tasks and functions, declaration, invocation, automatic tasks and functions Code converters, Flip-flops, counters, Shift registers, FIFOMoore and Mealy machine, Design and Analysis Introduction to logic synthesis, impact of logic synthesis, Verilog HDL constructs and operators for logic synthesis, synthesis design flow, verification of synthesized circuits, modeling tips, design partitioning. PERIODICAL - II Implementation Technology - PLDs, custom chips, standard cell and gate arrays
Logic implementation by macro, logic synthesis, logic optimization, Physical design for FPGAs Behavioral design, design methodology, busses, Platform FPGAs, Multi-FPGA systems, Novel architecture END SEM |
Handouts
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Downloads
Quiz Quiz 1 Quiz 1_Solution
Quiz 2 Quiz 2_Solution
Quiz 3 Quiz 3_Solution
Quiz 4 Quiz 4_Solution
Tutorials Tutorial#1
Question Paper
Mini Project Report Guidelines click here
Quiz Quiz 1 Quiz 1_Solution
Quiz 2 Quiz 2_Solution
Quiz 3 Quiz 3_Solution
Quiz 4 Quiz 4_Solution
Tutorials Tutorial#1
Question Paper
Mini Project Report Guidelines click here