16ES707 Multicore Architectures
Credits: 3
Credits: 3
THIS PAGE contains information about the elective course 16ES707 Multicore Architectures offered in the Second semester of 2017 - 2018 academic year. It tells you everything about this course, including its aim, syllabus, and operation.
· What is this course for?
· What you will learn
· Lecture schedule
· Assignments
· Supplementary materials
· References
What is this course for?
Multimedia, video and audio content are now part of mobile networks and hand-held mobile Internet devices. Real-time processing of video and audio streams demands computational performance of a few giga-operations per second, which cannot be obtained using a single processor. Such increasingly demanding modern applications including telecommunications networking require multiple processors to achieve computational performance. This necessity for speed and manageable power consumption makes it likely that the next generation of embedded processing systems will include hundreds of cores, while being increasingly programmable, blending processors and configurable hardware in a power-efficient manner.
What you will learn
The course begins with an overview of the evolution of multiprocessor architectures for embedded applications and necessary fundamentals to understand the concepts of multiple cores. It gives an insight into the architectural details like parallelism, scheduling, memory hierarchy and the technical challenges associated with increased integration of processors and multiple cores. It offers the physical details of both software and hardware in embedded architectures, as well as their limitations and potential for future growth.
Evaluation
Method of evaluation is by Continuous Assessment and an End-of-Semester examination.
Continuous Assessment - 50%
Periodical Test I - 15%
Periodical Test II - 15%
Quiz / Tutorial - 5%
Term Paper - 15%
End-of-Semester Examination - 50%
Suggested Readings
1. J.L. Hennessy and D.A. Patterson, “Computer Architecture: A Quantitative Approach”, Fifth Edition, Morgan Kaufmann, 2011.
2. Georgios Kornaros, “Multi-core Embedded Systems”, CRC Press, Taylor and Francis Group, 2010.
Lecture Schedule
· What is this course for?
· What you will learn
· Lecture schedule
· Assignments
· Supplementary materials
· References
What is this course for?
Multimedia, video and audio content are now part of mobile networks and hand-held mobile Internet devices. Real-time processing of video and audio streams demands computational performance of a few giga-operations per second, which cannot be obtained using a single processor. Such increasingly demanding modern applications including telecommunications networking require multiple processors to achieve computational performance. This necessity for speed and manageable power consumption makes it likely that the next generation of embedded processing systems will include hundreds of cores, while being increasingly programmable, blending processors and configurable hardware in a power-efficient manner.
What you will learn
The course begins with an overview of the evolution of multiprocessor architectures for embedded applications and necessary fundamentals to understand the concepts of multiple cores. It gives an insight into the architectural details like parallelism, scheduling, memory hierarchy and the technical challenges associated with increased integration of processors and multiple cores. It offers the physical details of both software and hardware in embedded architectures, as well as their limitations and potential for future growth.
Evaluation
Method of evaluation is by Continuous Assessment and an End-of-Semester examination.
Continuous Assessment - 50%
Periodical Test I - 15%
Periodical Test II - 15%
Quiz / Tutorial - 5%
Term Paper - 15%
End-of-Semester Examination - 50%
Suggested Readings
1. J.L. Hennessy and D.A. Patterson, “Computer Architecture: A Quantitative Approach”, Fifth Edition, Morgan Kaufmann, 2011.
2. Georgios Kornaros, “Multi-core Embedded Systems”, CRC Press, Taylor and Francis Group, 2010.
Lecture Schedule
Week
1
2 3 4 5 6 7 8 9 10 11 |
Topics
Review of Computer Design
Pipelining Pipelining Instruction Level Parallelism Instruction Level Parallelism Instruction Level Parallelism Thread-level parallelism Memory hierarchy design Storage Systems, Warehouse-Scale Computers Multicore Programming Environments Power Optimization in multicore Systems |
Keywords
Classes of computers, computer architecture, trends in technology, evolution of processor architecture, trends in power, energy and cost, performance measures
Basics of Pipelining, Hazards Pipeline implementation Periodical - I Basics of Instruction Level Parallelism, Branch Prediction Techniques, Dynamic scheduling Static & Dynamic Scheduling, Tomasulo's Algorithms Hardware based Speculation, Branch Target Buffers, Limits of ILP Periodical - II Multi-issue and Multi-core processors, Shared and Distributed memory Multiprocessor Architectures, Transaction Memory issues Cache coherence, Memory wall problem - Advanced Cache Memory design - Virtual Memory Advanced Topics in Disk Storage, Disk Arrays, Designing and Evaluating an I/O System - Internet Archive Cluster; Computer architecture of Warehouse-Scale computers Aurix Tricore Architecture and programming examples |
Handouts
|
Term Paper Guidelines (Weightage 15%)
Suggested topics
Suggested topics
- Multi-Core Embedded Wireless Sensor Networks
- Reconfigurable Architecture for Multicore Systems
- Rapid parallel SoC FPGA prototyping
- Multicore Node Performance in Wireless Sensor Network
- Vedic Multiplier Technique on Multicore Processor
- Multicore IoT Systems
- Performance Evaluation of Multi-core processors
- Multi2Sim Simulator
- MATLAB Parallel computing toolbox
- Benchmark suite